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| PD - 94543 AUTOMOTIVE MOSFET IRLR3915 IRLU3915 HEXFET(R) Power MOSFET D Features Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax G VDSS = 55V RDS(on) = 14m S Description Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this product are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. ID = 30A D-Pak IRLR3915 I-Pak IRLU3915 Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS EAS EAS (6 sigma) IAR EAR TJ TSTG Continuous Drain Current, VGS @ 10V (Silicon limited) Continuous Drain Current, VGS @ 10V (See Fig.9) Continuous Drain Current, VGS @ 10V (Package limited) Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Single Pulse Avalanche Energy Tested Value Avalanche Current Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 61 43 30 240 120 0.77 16 200 600 See Fig.12a, 12b, 15, 16 -55 to + 175 Units A W W/C V mJ A mJ C 300 (1.6mm from case ) Thermal Resistance Parameter RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount) Junction-to-Ambient--- Typ. --- --- 110 Max. 1.3 50 Units C/W HEXFET(R) is a registered trademark of International Rectifier. www.irf.com 1 09/06/02 IRLR/U3915 Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 55 --- --- --- 1.0 42 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- 0.057 12 14 --- --- --- --- --- --- 61 9.0 17 7.4 51 83 100 4.5 7.5 1870 390 74 2380 290 540 Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 14 VGS = 10V, ID = 30A m 17 VGS = 5.0V, ID = 26A 3.0 V VDS = 10V, ID = 250A --- S VDS = 25V, ID = 30A 20 VDS = 55V, VGS = 0V A 250 VDS = 55V, VGS = 0V, TJ = 125C 200 VGS = 16V nA -200 VGS = -16V 92 ID = 30A 14 nC VDS = 44V 25 VGS = 10V --- VDD = 28V ns --- ID = 30A --- RG = 8.5 --- VGS = 10V D Between lead, --- nH 6mm (0.25in.) G from package --- and center of die contact S --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 44V, = 1.0MHz --- VGS = 0V, VDS = 0V to 44V Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol --- --- 61 showing the A G integral reverse --- --- 240 p-n junction diode. S --- --- 1.3 V TJ = 25C, IS = 30A, VGS = 0V --- 62 93 ns TJ = 25C, IF = 30A, VDD = 25xjkl V --- 110 170 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLR/U3915 10000 TOP 1000 VGS 15V 10V 5.0V 3.0V 2.7V 2.5V 2.25V 2.0V TOP VGS 15V 10V 5.0V 3.0V 2.7V 2.5V 2.25V 2.0V ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 1000 100 BOTTOM 100 BOTTOM 10 1 0.1 0.01 0.001 0.1 1 10 100 1000 10 2.0V 1 2.0V 20s PULSE WIDTH Tj = 25C 0.1 0.1 1 20s PULSE WIDTH Tj = 175C 10 100 1000 VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000.00 70 G fs , Forward Transconductance (S) ID, Drain-to-Source Current () T J = 25C 60 50 40 30 20 10 0 TJ = 175C T J = 25C 100.00 T J = 175C 10.00 1.00 VDS = 25V 20s PULSE WIDTH 0.10 1.0 3.0 5.0 7.0 9.0 11.0 13.0 15.0 0 10 20 30 40 50 60 VGS, Gate-to-Source Voltage (V) ID,Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3 IRLR/U3915 100000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C SHORTED gs ds Crss = C gd Coss = Cds + Cgd VGS , Gate-to-Source Voltage (V) 8 12 I D = 30A VDS = 44V VDS = 27V VDS = 11V 10 10000 C, Capacitance(pF) Ciss 1000 6 Coss 100 4 Crss 2 10 1 10 100 0 0 10 20 30 40 50 60 70 VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000 1000 OPERATION IN THIS AREA LIMITED BY R DS (on) 100 TJ = 175 10 C ID, Drain-to-Source Current (A) I SD , Reverse Drain Current (A) 100 100sec 10 1msec Tc = 25C Tj = 175C Single Pulse 1 1 10 TJ = 25 1 C V GS = 0 V 0.1 0.0 0.5 1.0 1.5 2.0 10msec 100 1000 V SD ,Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U3915 70 2.5 LIMITED BY PACKAGE 60 2.0 I D = 61A 50 RDS(on) , Drain-to-Source On Resistance I D , Drain Current (A) (Normalized) 40 1.5 30 1.0 20 0.5 10 V GS = 10V 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0 25 50 75 100 125 150 175 TC , Case Temperature ( C) TJ , Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance vs. Temperature 10 (Z thJC ) 1 D = 0.50 Thermal Response 0.20 0.10 0.1 0.05 t1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1 / t 2 +TC 1 t2 P DM J = P DM x Z thJC 0.1 t1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U3915 15V 500 TOP L ID 12A 21A 30A RG 20V VGS D.U.T IAS tp + V - DD E AS , Single Pulse Avalanche Energy (mJ) VDS DRIVER 400 BOTTOM 300 A 0.01 200 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 100 0 25 50 75 100 125 150 175 Starting Tj, Junction Temperature ( C) I AS Fig 12b. Unclamped Inductive Waveforms QG Fig 12c. Maximum Avalanche Energy vs. Drain Current 10 V QGS VG QGD VGS(th) Gate threshold Voltage (V) 2.0 1.5 Charge Fig 13a. Basic Gate Charge Waveform Current Regulator Same Type as D.U.T. ID = 250A 1.0 50K 12V .2F .3F D.U.T. VGS 3mA + V - DS 0.5 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6 www.irf.com IRLR/U3915 1000 Duty Cycle = Single Pulse Avalanche Current (A) 100 0.01 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses 10 0.05 0.10 1 0.1 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs.Pulsewidth 220 200 EAR , Avalanche Energy (mJ) 180 160 140 120 100 80 60 40 20 0 25 50 TOP Single Pulse BOTTOM 10% Duty Cycle ID = 30A 75 100 125 150 Starting T J , Junction Temperature (C) Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. 175 D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*t av Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com 7 IRLR/U3915 D.U.T Driver Gate Drive + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs RD VDS V GS RG 10V Pulse Width 1 s Duty Factor 0.1 % D.U.T. + -V DD Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com IRLR/U3915 D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN -B1.52 (.060) 1.15 (.045) 1.14 (.045) 0.76 (.030) 0.89 (.035) 3X 0.64 (.025) 0.25 (.010) M AMB NOTES: 2X 0.58 (.023) 0.46 (.018) 2.28 (.090) 4.57 (.180) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN THE AS S EMBLY LINE "A" PART NUMBER INT ERNATIONAL RECTIFIER LOGO IRF U120 12 916A 34 AS S EMBLY LOT CODE DATE CODE YEAR 9 = 1999 WEEK 16 LINE A www.irf.com 9 IRLR/U3915 I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 6.22 (.245) 5.97 (.235) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 3X 1.14 (.045) 0.76 (.030) 3X 0.89 (.035) 0.64 (.025) M AMB 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 2.28 (.090) 2X 0.25 (.010) I-Pak (TO-251AA) Part Marking Information 10 www.irf.com IRLR/U3915 D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L = 0.45mH, RG = 25, IAS = 30A, VGS =10V. Part not recommended for use above this value. ISD 30A, di/dt 280A/s, VDD V(BR)DSS, TJ 175C. Pulse width 1.0ms; duty cycle 2%. Notes: Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/02 www.irf.com 11 |
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